EEPROM cell with charge loss
US9165775B2 · kind B2 · utility
1Cited by
7References
18Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Dec 31, 2008 |
| Grant date | Oct 20, 2015 |
| Priority date | — |
| Expiry date | Feb 8, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/693
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An EEPROM memory cell that includes a dual-gate MOS transistor in which the two gates are separated by an insulation layer, wherein the insulation layer includes a first portion and a second portion having lower insulation properties than the first one, the second portion being located at least partially above a channel area of the transistor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.