Semiconductor devices including insulating extension patterns between adjacent landing pads and methods of fabricating the same
US9165934B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 29, 2014 |
| Grant date | Oct 20, 2015 |
| Priority date | — |
| Expiry date | Jul 29, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor memory device includes a plurality of pattern structures respectively including a bit line and insulating spacers on sidewalls thereof protruding from a substrate. A plurality of insulating extension patterns are provided on opposing sidewalls of the pattern structures, and respectively extend from upper portions of the opposing sidewalls toward the substrate along the insulating spacers such that lower portions of the opposing sidewalls are free of the extension patterns. A plurality of buried contact patterns are provided on the substrate between the lower portions of the opposing sidewalls of adjacent pattern structures. Related fabrication methods are also discussed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.