Array substrate and method for manufacturing the same
US9165955B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 21, 2012 |
| Grant date | Oct 20, 2015 |
| Priority date | — |
| Expiry date | Sep 6, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D86/0221
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Disclosed herein is a method for manufacturing an array substrate. The method includes forming a source electrode and a drain electrode on a substrate. A semiconductor layer, an organic insulating layer, and a gate electrode layer are sequentially formed to cover the substrate, the source electrode, and the drain electrode. A patterned photoresist layer is formed on the gate electrode layer. The exposed portion of the gate electrode layer, and a portion of the organic insulative layer and a portion of the semiconductor layer thereunder are removed to form a gate electrode. An organic passivation layer is formed on the gate electrode, the source electrode, and the drain electrode. The organic passivation layer has a contact window to expose a portion of the drain electrode. A pixel electrode is formed on the organic passivation layer and the exposed portion of the drain electrode.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.