Array substrate and manufacturing method thereof
US9165956B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 16, 2013 |
| Grant date | Oct 20, 2015 |
| Priority date | — |
| Expiry date | Apr 18, 2034 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG02F1/136236
- WIPO fieldOptics
- WIPO sectorInstruments
Abstract
Embodiments of the present invention relate to an array substrate and a manufacturing method thereof. The manufacturing method comprises: step 1: forming a gate line, a gate electrode, a first insulating layer, an active layer and ohmic contact layers on a base substrate by a first patterning process using a gray-tone or half-tone mask, in which the active layer between the ohmic contact layers corresponds to a channel region; step 2: forming a second insulating layer and a pixel electrode film on the base substrate obtained after the step 1 by a second patterning process using a gray-tone or half-tone mask; and step 3: forming a drain electrode, a source electrode, a data line and a passivation layer on the base substrate obtained after the step 2 by a third patterning process using a gray-tone or half-tone mask.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.