3D-stacked backside illuminated image sensor and method of making the same
US9165968B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 14, 2012 |
| Grant date | Oct 20, 2015 |
| Priority date | — |
| Expiry date | Aug 10, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10F39/813
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A stacked image sensor and method for making the same are provided. The stacked image sensor includes an upper chip with a pixel array thereon. The second chip includes a plurality of column circuits and row circuits associated with the columns and rows of the pixel array and disposed in respective column circuit and row circuit regions that are arranged in multiple groups. Inter-chip bonding pads are formed on each of the chips. The inter-chip bonding pads on the second chip are arranged linearly and are contained within the column circuit regions and row circuit regions in one embodiment. In other embodiments, the inter-chip bonding pads are staggered with respect to each other. In some embodiments, the rows and columns of the pixel array include multiple signal lines and the corresponding column circuit regions and row circuit regions also include multiple inter-chip bonding pads.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.