Relaxation oscillator
US9166569B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 28, 2014 |
| Grant date | Oct 20, 2015 |
| Priority date | — |
| Expiry date | Jan 28, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K4/501
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A relaxation oscillator is provided in the present invention. The relaxation oscillator includes a R-S latch, a first delay circuit and a second delay circuit. The input terminal of the first delay circuit is coupled to the Q output terminal of the R-S latch, and the output terminal of the first delay circuit is coupled to the reset terminal of the R-S latch. The input terminal of the second delay circuit is coupled to the inversion Q output terminal of the R-S latch, and the output terminal of the second delay circuit is coupled to the set terminal of the R-S latch. When the input terminal of the first delay circuit inputs a first logic voltage, after a delay time, the output terminal of the first delay circuit outputs a second logic pulse. When the input terminal of the second delay circuit inputs the first logic voltage, after the delay time, the output terminal of the second delay circuit outputs the second logic pulse.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.