Memory control apparatus, information processing apparatus, and memory control method
US9166933B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 5, 2012 |
| Grant date | Oct 20, 2015 |
| Priority date | — |
| Expiry date | Aug 6, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L49/901
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A memory control apparatus that controls writing and reading of data to/from a memory. The memory control apparatus includes: a sequence control unit that receives a packet sequence including a write packet including a write request of data and a read packet including a read request of the data, and changes an arrangement of the write packet and the read packet included in the packet sequence so that a first predetermined number of write packets are arranged successively and a second predetermined number of read packets are arranged successively; and a command output unit that receives the packet sequence from the sequence control unit, and outputs a write command according to the write packet and an a read command according to the read packet to the memory, in accordance with an order of arrangement of the write packet and the read packet.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.