Enhancing processing efficiency in large instruction width processors
US9170816B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 15, 2009 |
| Grant date | Oct 27, 2015 |
| Priority date | — |
| Expiry date | Dec 22, 2030 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3893
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A processor includes one or more processing units, an execution pipeline and control circuitry. The execution pipeline includes at least first and second pipeline stages that are cascaded so that program instructions, specifying operations to be performed by the processing units in successive cycles of the pipeline, are fetched from a memory by the first pipeline stage and conveyed to the second pipeline stage, which causes the processing units to perform the specified operations. The control circuitry is coupled, upon determining that a program instruction that is present in the second pipeline stage in a first cycle of the pipeline is to be executed again in a subsequent cycle of the pipeline, to cause the execution pipeline to reuse the program instruction in one of the pipeline stages without re-fetching the program instruction from the memory.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.