Parallel processing of data
US9170848B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 27, 2011 |
| Grant date | Oct 27, 2015 |
| Priority date | — |
| Expiry date | May 14, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L67/1097
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Parallel processing of data may include a set of map processes and a set of reduce processes. Each map process may include at least one map thread. Map threads may access distinct input data blocks assigned to the map process, and may apply an application specific map operation to the input data blocks to produce key-value pairs. Each map process may include a multiblock combiner configured to apply a combining operation to values associated with common keys in the key-value pairs to produce combined values, and to output intermediate data including pairs of keys and combined values. Each reduce process may be configured to access the intermediate data output by the multiblock combiners. For each key, an application specific reduce operation may be applied to the combined values associated with the key to produce output data.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.