Solid state device coding architecture for chipkill and endurance improvement
US9170881B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 30, 2014 |
| Grant date | Oct 27, 2015 |
| Priority date | — |
| Expiry date | Apr 30, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M13/152
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A first decoder performs decoding on each data set in a first plurality of data sets using a first code; each data set in the first plurality is stored on a different chip. It is determined if the first decoding is successful; if not, a second decoder performs a second decoding on each data set in a second plurality of data sets using a second code; each data set in the second plurality includes at least some data, after the first decoding using the first code, from each data set in the first plurality. The first decoder performs a third decoding on each data set in the first plurality using the first code, where each data set in the first plurality includes at least some data, after the second decoding using the second code, from each data set in the second plurality.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.