Wear-level of cells/pages/sub-pages/blocks of a memory
US9170933B2 · kind B2 · utility
9Cited by
5References
18Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jun 6, 2011 |
| Grant date | Oct 27, 2015 |
| Priority date | — |
| Expiry date | May 21, 2032 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/7211
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method for wear-leveling cells, pages, sub-pages or blocks of a memory such as a flash memory includes receiving (S10) a chunk of data to be written on the cell, page, sub-page or block of the memory; counting (S40), in the received chunk of data, a number of times a given type of binary data ‘0’ or ‘1’ is to be written; and distributing (S50) the writing of the received chunk of data among cells, pages, sub-pages or blocks of the memory such as to wear-level the memory with respect to the number of the given type of binary data ‘0’ or ‘1’ counted in the chunk of data to be written.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.