Cached PHY register data access
US9170969B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Jan 20, 2013 |
| Grant date | Oct 27, 2015 |
| Priority date | — |
| Expiry date | Jan 20, 2033 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/4282
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Ethernet physical sublayer (PHY) devices each provide PHY register data. One or more of the Ethernet PHY devices are connected to each of one or more management data input/output (MDIO)/management data clock (MDC) interfaces to which a number of MDIO/MDC controllers are connected. Each MDIO/MDC controller polls a corresponding MDIO/MDC interface to receive the PHY register data from the one or more Ethernet PHY devices connected thereto. The MDIO/MDC controllers store portions of the PHY register data received from the Ethernet PHY devices to a memory to which an interface is connected. A processor connected to the interface accesses the portions of the PHY register data stored to the memory. The processor can retrieve the portions of the PHY register data over the interface more quickly than the MDIO/MDC controllers can retrieve the PHY register data over the MDIO/MDC interfaces.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.