High speed overlay of idle I2C bus bandwidth
US9170975B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 3, 2013 |
| Grant date | Oct 27, 2015 |
| Priority date | — |
| Expiry date | Jan 10, 2034 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2213/0016
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
High-speed serial communications between programmable devices connected to an I2C bus that includes a serial clock channel (SCL) and a serial data channel (SDA), having at least a logical low state and a logical high state. The programmable device determines if the SCL channel is idle, indicated by a logical high state. Determining the SCL to be idle, the programmable device holds the SCL to a logical low state. The programmable device operates high-speed serial communications using the SDA channel while holding the SCL to the low logical state. In response to completion of the high-speed communications, the programmable device releases the SCL channel and the SCL channel returns to the logical high state.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.