Hardware emulation method and system using a port time shift register
US9171111B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 29, 2014 |
| Grant date | Oct 27, 2015 |
| Priority date | — |
| Expiry date | Sep 29, 2034 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2117/08
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A processor-based hardware functional verification system with time shift registers is described. The system includes a processor cluster with a plurality of processors that each have a data inputs and select inputs. Furthermore, a plurality of electronic memories each having a plurality of read ports is associated with the processors, respectively. The time shift registers each have an input in communication with the read ports of the electronic memories and an output in communication with the select inputs of the processors. The system further includes an instruction memory that provides a control signal to each of the time shift registers to store data output from read ports of the electronic memories that can be provided to the processor for evaluation during a subsequent emulation step.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.