Semiconductor memory device and method for controlling the same
US9171631B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 15, 2013 |
| Grant date | Oct 27, 2015 |
| Priority date | — |
| Expiry date | Feb 18, 2034 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/30
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
According to one embodiment, a semiconductor memory device includes a first transistor, a detector, and a second transistor. The first transistor is capable of transferring a first voltage to a bit line. The detector reads data held by a memory cell connected to the bit line. The second transistor is capable of transferring a second voltage and a third voltage to the detector. The second voltage is generated by a source different from a source of the first voltage. The third voltage is larger than the second voltage. The second transistor charges the detector to one of the second voltage and the third voltage, while the first transistor transferring the first voltage to the bit line.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.