Sampling network
US9171642B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 23, 2014 |
| Grant date | Oct 27, 2015 |
| Priority date | — |
| Expiry date | May 23, 2034 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C27/024
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A circuit with a sampling network may include a pair of capacitors, where each of the capacitors has a first node and a second node; a first pair of switches communicatively coupling corresponding differential input voltage signals to the first node of each of the capacitors; and a second pair of switches communicatively coupling the second node of each of the capacitors to a common mode voltage source. Corresponding differential output voltage signals at the second node of each of the capacitors may be communicatively coupled using a differential switch. The second pair of switches may be coupled in parallel with the differential switch. A clock signal of the differential switch may be de-asserted prior to de-asserting corresponding clock signals for each of the second pair of switches.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.