Address windowing for at-speed bitmapping with memory built-in self-test
US9171645B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 28, 2013 |
| Grant date | Oct 27, 2015 |
| Priority date | — |
| Expiry date | Dec 12, 2033 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2029/4402
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Integrated circuits with memory built-in self-test (BIST) logic and methods of testing using the same are disclosed. The method includes setting an address window for locating defects in a memory array. The method further includes comparing output data of the memory array to expected data to determine that a defect exists at location “M” in the memory array within the address window. The method further includes storing, in registers, the address M and a resultant bit fail vector associated with the location “M” of the defect found in the memory array. The method further includes resetting the registers to a null value and resetting the address window with a new minimum and maximum address pair, to compare the output data of the memory array to the expected data within the reset address window which excludes address M.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.