High efficiency on-chip 3D transformer structure
US9171663B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 25, 2013 |
| Grant date | Oct 27, 2015 |
| Priority date | — |
| Expiry date | Jul 25, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01F2027/2809
- WIPO fieldElectrical machinery, apparatus, energy
- WIPO sectorElectrical engineering
Abstract
An integrated circuit transformer structure includes at least two conductor groups stacked in parallel in different layers. A first spiral track is formed in the at least two conductor groups, the first spiral track includes first turns of a first radius within each of the at least two conductor groups, and second turns of a second radius within each of the at least two conductor groups, the first and second turns being electrically connected. A second spiral track is formed in the at least two conductor groups, the second spiral track including a plurality of adjacent turns of one or more radii within each of the at least two conductor groups and disposed in a same plane between the first and second turns in each of the at least two conductor groups.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.