Semiconductor device having a trench gate structure and manufacturing method of the same
US9171906B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 15, 2014 |
| Grant date | Oct 27, 2015 |
| Priority date | — |
| Expiry date | May 15, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/516
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
In a manufacturing method of a semiconductor device, a trench is defined in a semiconductor substrate, and an adjuster layer having a first conductivity type impurity concentration higher than a drift layer is formed at a portion of the semiconductor substrate adjacent to a bottom wall of the trench. A channel layer is formed by introducing second conductivity type impurities to a portion of the semiconductor substrate adjacent to a sidewall of the trench and between the adjustment layer and a main surface of the semiconductor substrate while restricting the channel layer from extending in a depth direction of the trench by the adjustment layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.