Cascode bias of power MOS transistors
US9172339B2 · kind B2 · utility
3Cited by
2References
13Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 20, 2013 |
| Grant date | Oct 27, 2015 |
| Priority date | — |
| Expiry date | Dec 20, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03F2203/7236
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
There is disclosed a driver circuit for a power amplifier of class D type having a segmented architecture with at least one current branch which can be powered down in a low power mode of operation of the circuit. The branch comprising a switch with a cascode MOS transistor, the circuit further comprises a bias circuitry adapted for dynamically generating a dynamic bias control signal so as to cause the cascode MOS transistor of the switch to be ‘Off’ in the low power mode.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.