High speed interleaved ADC with compensation for DC offset mismatch
US9172388B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 10, 2015 |
| Grant date | Oct 27, 2015 |
| Priority date | — |
| Expiry date | Jun 10, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M1/1215
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An analog to digital conversion device with DC offset mismatch compensation comprises a composite analog to digital converter (ADC) consisting of N interleaved sub-ADCs, a DC offset accumulator, an averaging unit, a subtraction unit, and a compensation unit. The ADC generates a stream of digital samples corresponding to signal values at an analog input to the ADC. The digital stream is a combination of N partial signals produced by the respective sub-ADCs. The DC offset accumulator measures and stores DC offsets of the respective partial signals. The averaging unit calculates an average value of DC offsets of the respective N partial signals. The subtraction unit is responsive to the DC offsets of the respective partial signals and the average value of the DC offsets, to produce a signal representative of the differences between the values arriving at a DC offset input and the value arriving at an average value input. The subtraction unit is responsive to the DC offsets of the respective partial signals and the average value of the DC offsets, to produce a signal representative of the differences between the values arriving at the DC offset input and the value arriving at the avera…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.