Methods and apparatus for frame detection
US9172505B1 · kind B1 · utility
1Cited by
2References
23Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Sep 21, 2012 |
| Grant date | Oct 27, 2015 |
| Priority date | — |
| Expiry date | Dec 13, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L1/0041
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
One embodiment relates to a frame detection circuit for detecting a frame boundary. The circuit includes at least two frame buffers and a staged-parallel structure of syndrome computation circuits that computes a number of syndromes in one cycle. The two frame buffers are each one word in width. The number of syndromes computed in one cycle by the cascaded series is a fraction of a number of bits in one word. Another embodiment relates to a method for detecting a frame boundary. Another embodiment relates to a method for computing a current syndrome. Other embodiments, aspects, and features are also disclosed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.