Tunable delay cells for time-to-digital converter
US9176479B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 23, 2014 |
| Grant date | Nov 3, 2015 |
| Priority date | — |
| Expiry date | Jan 24, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M1/50
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A time-to-digital converter (TDC) comprises a first delay line including a plurality of first delay cells connected in series, wherein each of the first delay cells include a plurality of first delay units connected in series, wherein each of the first delay units includes a tunable PMOS transistor, a first poly on oxide definition (OD) edge (PODE) transistor, and a pull-up PMOS transistor. The TDC further comprises a second delay line including a plurality of second delay cells connected in series, wherein each of the second delay cells include a plurality of second delay units connected in series, wherein each of the second delay units includes a tunable NMOS transistor, a second PODE transistor, and a pull-down NMOS transistor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.