System and method for controlling central processing unit power with guaranteed transient deadlines
US9176572B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 5, 2013 |
| Grant date | Nov 3, 2015 |
| Priority date | — |
| Expiry date | Jul 5, 2033 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Methods, systems and devices that include a dynamic clock and voltage scaling (DCVS) solution configured to compute and enforce performance guarantees for a group of processors to ensure that the processors does not remain in a busy state (e.g., due to transient workloads) for a combined period that is more than a predetermined amount of time above that which is required for one of the processors to complete its pre-computed steady state workload. The DCVS may adjust the frequency and/or voltage of one or more of the processors based on a variable delay to ensure that the multiprocessor system only falls behind its steady state workload by, at most, a predefined maximum amount of work, irrespective of the operating frequency or voltage of the processors.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.