Cache memory system for tile based rendering and caching method thereof
US9176880B2 · kind B2 · utility
5Cited by
8References
13Claims
0Family size
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Key dates
| Filing date | Oct 16, 2012 |
| Grant date | Nov 3, 2015 |
| Priority date | — |
| Expiry date | May 28, 2033 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A cache memory system and a caching method for a tile-based rendering may be provided. Each of cache lines in the cache memory system may include delayed-replacement information. The delayed-replacement information may indicate whether texture data referred to at a position of an edge of a tile is included in a cache line. When a cache line corresponding to an access-requested address is absent in the cache memory system, the cache memory system may select and remove a cache line to be removed from an associative cache unit, based on delayed-replacement information.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.