In-hierarchy circuit analysis and modification for circuit instances
US9177090B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Sep 10, 2014 |
| Grant date | Nov 3, 2015 |
| Priority date | — |
| Expiry date | Sep 10, 2034 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2119/12
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Modifying a hierarchical circuit design includes accessing hierarchical circuit data in a hierarchical circuit design comprising top level block data and lower level block data; performing timing analysis on a selected portion of the hierarchical circuit data to determine whether timing closure is achieved; and in the event that timing closure is not achieved, determining, within a top level design process, an optimization move on the selected portion of the hierarchical circuit data; wherein the selected portion of the hierarchical circuit data includes a selected portion of the top level block data and a selected portion of the lower level block data.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.