Row formation during datapath placement in circuit design
US9177091B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 5, 2014 |
| Grant date | Nov 3, 2015 |
| Priority date | — |
| Expiry date | Mar 23, 2034 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2119/12
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Implementations of the present disclosure involve methods and systems for component placement in a datapath block of a microelectronic circuit design. In particular, implementations provide for collecting groups of common components in the datapath block that form a row or partial row. A preliminary layout of the datapath block is performed with the component set rows and any other components of the datapath block design. Common components are then collected into groups or sets to form additional rows within the datapath layout, with at least some consideration to the wire lengths between components in the rows. By collecting common components into rows with consideration to the wire lengths between interconnected components, the timing performance of the datapath block may be improved.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.