Memory generating method of memory compiler and generated memory
US9177624B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 22, 2014 |
| Grant date | Nov 3, 2015 |
| Priority date | — |
| Expiry date | Sep 22, 2034 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2029/1202
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory includes a logic controller, a word line driver, a boost circuit, plural capacitor circuits, plural memory cores, plural selectors, and plural output drivers. The logic controller generates a word line enabling signal and a boost enabling signal. The word line driver receives the word line enabling signal. The boost circuit receives the boost enabling signal. The plural capacitor circuits are connected between the boost circuit and the word line driver. Each of the plural memory cores is connected with the word line driver through plural word lines. The plural selectors are connected with the corresponding memory cores. The plural output drivers are connected with the corresponding selectors. The number of the plural memory cores is positively correlated with the number of the plural capacitor circuits.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.