Memory with bit line capacitive loading
US9177671B2 · kind B2 · utility
1Cited by
32References
16Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Feb 23, 2012 |
| Grant date | Nov 3, 2015 |
| Priority date | — |
| Expiry date | Dec 30, 2033 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2029/5002
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory that may allow for the detection of weak data storage cells may include data storage cells, a column multiplexer, a sense amplifier, and a load circuit. The load circuit may include one or more capacitive loads and may be operable to controllably select one or more of the capacitive loads to couple to the input of the sense amplifier.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.