Trench MOS device having a termination structure with multiple field-relaxation trenches for high voltage applications
US9178015B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 10, 2014 |
| Grant date | Nov 3, 2015 |
| Priority date | — |
| Expiry date | Mar 11, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/117
Abstract
A termination structure for a semiconductor device includes a semiconductor substrate having an active region and a termination region. Two or more trench cells are located in the termination region and extend from a boundary of the active region toward an edge of the semiconductor substrate. A termination trench is formed in the termination region on a side of the trench cells remote from the active region. A conductive spacer is located adjacent to a sidewall of the termination trench nearest the trench cells. A first oxide layer is formed in the termination trench and contacts a sidewall of the conductive spacer. A first conductive layer is formed on a backside surface of the semiconductor substrate. A second conductive layer is formed atop the active region and the termination region.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.