Array substrate and manufacturing method thereof
US9178046B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Sep 26, 2012 |
| Grant date | Nov 3, 2015 |
| Priority date | — |
| Expiry date | Dec 27, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D86/0231
Abstract
Embodiment of the present invention disclose an array substrate and a manufacturing method thereof, and the manufacturing method of an array substrate comprises the following steps: Step S1: a gate electrode metal layer, an insulating layer and an active layer are deposited successively on a substrate, and gate electrodes, gate lines and an active layer pattern are formed through a first mask process; Step S2: a protective layer is deposited on the substrate after completion of the step S1, and via-holes are formed in the protective layer through a second mask process; and Step S3: a pixel electrode layer and a source/drain electrode metal layer are deposited sequentially on the substrate after completion of the step S2, and source/drain electrodes, pixel electrodes and data lines are formed through a third mask process.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.