Single photon avalanche diode for CMOS circuits
US9178100B2 · kind B2 · utility
Assignees
Inventors
Key dates
| Filing date | Sep 8, 2011 |
| Grant date | Nov 3, 2015 |
| Priority date | — |
| Expiry date | Sep 8, 2031 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02P70/50
Abstract
A single photon avalanche diode for use in a CMOS integrated circuit includes a deep n-well region formed above a p-type substrate and an n-well region formed above and in contact with the deep n-well region. A cathode contact is connected to the n-well region via a heavily doped n-type implant. A lightly doped region forms a guard ring around the n-well and deep n-well regions. A p-well region is adjacent to the lightly doped region. An anode contact is connected to the p-well region via a heavily doped p-type implant. The junction between the bottom of the deep n-well region and the substrate forms a multiplication region when an appropriate bias voltage is applied between the anode and cathode and the guard ring breakdown voltage is controlled with appropriate control of the lateral doping concentration gradient such that the breakdown voltage is higher than that of the multiplication region.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.