Wafer-level light emitting diode structure, light emitting diode chip, and method for forming the same
US9178107B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 3, 2011 |
| Grant date | Nov 3, 2015 |
| Priority date | — |
| Expiry date | Jun 23, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10H20/84
Abstract
A method for fabricating a wafer-level light emitting diode structure is provided. The method includes: providing a substrate, wherein a first semiconductor layer, a light emitting layer, and a second semiconductor layer are sequentially disposed on the substrate; subjecting the first semiconductor layer, the light emitting layer, and the second semiconductor layer with a patterning process to form a first depressed portion, a second depressed portion, a stacked structure disposed on the second depressed portion and a remained first semiconductor layer disposed on the depressed portion, wherein the stacked structure comprises a patterned second semiconductor layer, a patterned emitting layer, and a patterned first semiconductor layer; forming a first electrode on the remained first semiconductor layer of the first depressed portion; and forming a second electrode correspondingly disposed on the patterned second semiconductor layer of the second depressed portion.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.