Envelope detector with enhanced linear range
US9178476B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 26, 2012 |
| Grant date | Nov 3, 2015 |
| Priority date | — |
| Expiry date | Dec 26, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03F2203/45138
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
An envelope detector (ED) includes a voltage-mode ED core including parallel detection transistors for detecting a voltage envelope of an RF signal input. The detection transistors are configured with a size and for a current such that the transistors are biased in subthreshold regions of operation. The ED core is configured to variably control a bias current through the detection transistors, where the bias current is varied according to a voltage amplitude of the RF signal input to enhance a linear range of the ED while detection transistors continue to operate in subthreshold regions. A linearizer circuit may be configured to control the bias current based on feedback inputs from ED outputs. Several gain-programmable voltage amplifiers, which may include a final specialized class-AB amplifier, precede the ED core, to adapt a transmitter output voltage to an input range of the ED core, which extends the linear range of the ED.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.