Fast settling mixed signal phase interpolator with integrated duty cycle correction
US9178521B2 · kind B2 · utility
2Cited by
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20Claims
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Key dates
| Filing date | Feb 28, 2014 |
| Grant date | Nov 3, 2015 |
| Priority date | — |
| Expiry date | Feb 28, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L7/0337
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Described is an apparatus which comprises: a current steering digital-to-analog converter (DAC) to receive a digital bus to control current steering; a switch capacitor network to integrate currents from the DAC, the switch capacitor network having switches which are controllable by a plurality of digital clock signals; an output stage to compare the integrated currents against at least two threshold voltages and to generate an output signal; and a duty cycle corrector (DCC) operable to adjust the at least two threshold voltages to modify duty cycle of the output signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.