Systems and methods for controlling branch latency within computing applications
US9182949B2 · kind B2 · utility
10Cited by
7References
20Claims
0Family size
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Key dates
| Filing date | Mar 15, 2013 |
| Grant date | Nov 10, 2015 |
| Priority date | — |
| Expiry date | May 9, 2033 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/5072
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Systems and methods for controlling branch latency within computing applications including a development framework, a visual design subsystem, and a deployment subsystem, where at runtime the deployment subsystem is operable to implement out-of-band signaling mechanism such that components notify downstream components of accumulated branch latency so that downstream components can implement appropriate buffering techniques.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.