Method for simulation of partial VLSI ASIC design
US9183332B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 11, 2014 |
| Grant date | Nov 10, 2015 |
| Priority date | — |
| Expiry date | Apr 11, 2034 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/367
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A system and method for an automated way of running spice on a small portion of a design is presented. The system includes a sub-circuit netlist generation processor and an analog simulation processor. The sub-circuit netlist generation processor generates a sub-circuit netlist based, at least in part, on a HDL netlist, a parasitic capacitance database and trace rules. The sub-circuit netlist contains significantly fewer paths than the HDL netlist of an entire design so that its simulation time is much quicker. The analog simulation processor generates analog simulation results of the sub-circuit netlist based, at least in part, on dynamic inputs.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.