Systems and devices for quantum processor architectures
US9183508B2 · kind B2 · utility
36Cited by
28References
29Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Aug 7, 2014 |
| Grant date | Nov 10, 2015 |
| Priority date | — |
| Expiry date | Aug 7, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/195
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Quantum processor architectures employ unit cells tiled over an area. A unit cell may include first and second sets of qubits where each qubit in the first set crosses at least one qubit in the second set. Angular deviations between qubits in one set may allow qubits in the same set to cross one another. Each unit cell is positioned proximally adjacent at least one other unit cell. Communicatively coupling between qubits is realized through respective intra-cell and inter-cell coupling devices.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.