Method and apparatus for memory access
US9183908B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 30, 2012 |
| Grant date | Nov 10, 2015 |
| Priority date | — |
| Expiry date | Sep 5, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M13/6552
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An interleaver or deinterleaver comprises a memory having M logical memory units arranged in groups of N memory units such that accesses to memory units within a group are faster after a first access to a memory in that group using first access. An address generator is arranged to write consecutive data items a number of memory units apart that is less than the size of groups N of memory units so that two or more data items are written within groups. The arrangement provides fast interleaving without increasing memory size.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.