Detecting write disturb in multi-port memories
US9183947B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Apr 16, 2014 |
| Grant date | Nov 10, 2015 |
| Priority date | — |
| Expiry date | Apr 16, 2034 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C29/52
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A circuit comprises a memory cell, a first circuit, and a second circuit. The memory cell has a first control line and a second control line. The first control line carries a first control signal. The second control line carries a second control signal. The first circuit is coupled with the first control line, the second control line, and a node. The second circuit is coupled to the node and is configured to receive a first clock signal and a second clock signal. The first circuit and the second circuit, based on the first control signal, the second control signal, the first clock signal and the second clock signal, are configured to generate a node signal on the node. A logical value of the node signal indicates a write disturb condition of the memory cell.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.