Method for manufacturing integrated circuit devices, optical devices, micromachines and mechanical precision devices having patterned material layers with line-space dimensions of 50 nm and less
US9184057B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 29, 2012 |
| Grant date | Nov 10, 2015 |
| Priority date | — |
| Expiry date | Feb 29, 2032 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG03F7/405
- WIPO fieldOptics
- WIPO sectorInstruments
Abstract
A method for manufacturing integrated circuit devices, optical devices, micromachines and mechanical precision devices, the said method comprising the steps of (1) providing a substrate having patterned material layers having line-space dimensions of 50 nm and less and aspect ratios of >2; (2) providing the surface of the patterned material layers with a positive or a negative electrical charge by contacting the substrate at least once with an aqueous, fluorine-free solution S containing at least one fluorine-free cationic surfactant A having at least one cationic or potentially cationic group, at least one fluorine-free anionic surfactant A having at least one anionic or potentially anionic group, or at least one fluorine-free amphoteric surfactant A; and (3) removing the aqueous, fluorine-free solution S from the contact with the substrate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.