Semiconductor device and method of forming the same
US9184091B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 10, 2013 |
| Grant date | Nov 10, 2015 |
| Priority date | — |
| Expiry date | Feb 7, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B12/488
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
First dopant regions and second dopant regions are provided at both sides of the gate structures. Conductive lines cross over the gate structures and are connected to the first dopant regions. Each of the conductive lines includes a conductive pattern and a capping pattern disposed on the conductive pattern. Contact structures are provided between the conductive lines and are connected to the second dopant regions. Each of the contact structures includes a lower contact pattern disposed on the second dopant region and an upper contact pattern disposed on the lower contact pattern. A bottom surface of the upper contact pattern is lower than a top surface of the conductive pattern.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.