Three dimensional semiconductor memory device and method of manufacturing the same
US9184302B2 · kind B2 · utility
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2References
8Claims
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Key dates
| Filing date | Feb 12, 2013 |
| Grant date | Nov 10, 2015 |
| Priority date | — |
| Expiry date | Feb 12, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Provided is a three dimensional semiconductor device. The device may include mold layers vertically and sequentially stacked, a conductive pattern between the stacked mold layers, a plugging pattern vertically penetrating the stacked mold layers, an intermediate pattern between the conductive pattern and the plugging pattern, and protective layer patterns between the mold layers and the plugging pattern, wherein the protective layer patterns are separated by the intermediate pattern.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.