High-speed low-latency current-steering DAC
US9184764B1 · kind B1 · utility
1Cited by
4References
8Claims
0Family size
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Key dates
| Filing date | Sep 8, 2014 |
| Grant date | Nov 10, 2015 |
| Priority date | — |
| Expiry date | Sep 8, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M1/745
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A digital to analog converter (DAC) includes a quantity of N cells including a Least Significant Bit (LSB) cell, a Most Significant Bit (MSB) cell and, N−2 cells ordered therebetween. Each of the N cells is configured to carry a current of I, 2*I, 4*I, 8*I, . . . , 2^(N−1)*I, respectively. At least the LSB cell includes a first cell element and a second cell element driven by a first current input and a second current input, respectively. A difference between a magnitude of the first current input and a magnitude of the second input current is approximately equal to I.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.