Programmable signal processing circuit and method of demodulating via a demapping instruction
US9184953B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 13, 2005 |
| Grant date | Nov 10, 2015 |
| Priority date | — |
| Expiry date | Feb 22, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L27/38
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A programmable signal processing circuit has an instruction processing circuit (23, 24. 26), which has an instruction set that comprises a demapping instruction. The instruction processing circuit (23, 24, 26) has an operand input (30a) for receiving a complex number operand of the demapping instruction from a register file (22) and a result output (34) for writing a demapping result of the demapping instruction to the register file (22). The instruction processing circuit (23, 24, 26) determines at least four bit metrics in response to the demapping instruction, each indicating a relative position of the complex number relative to respective border line in a complex plane. The instruction processing circuit (23, 24, 26) writes a combination of the at least four bit metrics together to the result output (34) in the demapping result.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.