Method and apparatus for memory power reduction
US9189050B1 · kind B1 · utility
4Cited by
2References
11Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Aug 19, 2011 |
| Grant date | Nov 17, 2015 |
| Priority date | — |
| Expiry date | Mar 16, 2033 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method and system for reducing memory power usage are disclosed. The method and system comprise receiving at least one low-priority command and delaying execution of the at least one low-priority command until a predetermined event occurs, wherein the memory remains in a low-power mode until the predetermined event occurs.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.