Noncontiguous representation of an array
US9189382B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | May 8, 2013 |
| Grant date | Nov 17, 2015 |
| Priority date | — |
| Expiry date | Jan 21, 2034 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/023
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A system and method for storing a composite array including a reference array and one or more arraylets is provided. A set of contiguous memory locations for a reference array including one or more slots is allocated based on a quantity of bits in a binary representation of a logical array length. Each slot in the reference array corresponds to a position of a bit in the binary representation. For each bit corresponding to a slot that is determined to satisfy a condition, a set of contiguous memory locations is allocated for an arraylet, and a reference from the slot to the arraylet is provided. A largest arraylet having a greatest length of the allocated arraylets is identified, and a slice of adjacent data elements corresponding to a beginning of the logical array is placed into the largest arraylet.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.