Combined memory and storage tiering
US9189387B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 24, 2013 |
| Grant date | Nov 17, 2015 |
| Priority date | — |
| Expiry date | Apr 3, 2034 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/465
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Techniques for combined memory and storage tiering. For example, in one example, a method for managing placement of data in a data memory and storage system environment including at least one host computing device and at least one storage array includes the following steps. A memory and storage tier architecture is maintained across the data memory and storage system environment including one or more tiers resident on the host computing device and one or more tiers resident on the storage array. A user is enabled to: (i) specify on which of the one or more tiers resident on the host computing device and the one or more tiers resident on the storage array to store data associated with the execution of an application program; and/or (ii) specify a level of service by which the system automatically manages which of the one or more tiers resident on the host computing device and the one or more tiers resident on the storage array to store data associated with the execution of the application program.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.