Continuous tuning of preamble release timing in a double data-rate memory device interface
US9190129B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 31, 2013 |
| Grant date | Nov 17, 2015 |
| Priority date | — |
| Expiry date | Sep 29, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L7/0041
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Preamble release training in a double data-rate dynamic random access memory interface uses feedback from read operations to adjust the preamble release signal so that the preamble release signal continues to be activated close to the middle of the preamble. A first signal, and then a second signal, are generated in response to an initiation of a read operation. The first and second signals are characterized by a delay from the initiation of the read operation of one or more clock cycles plus a fine delay contributed by an adjustable delay circuit. The first signal is provided to a data strobe parking circuit that uses it to release or un-park the data strobe signal lines. The second signal is phase-compared with the data strobe signal associated with incoming data during the read operation. The adjustable delay circuit is adjusted in response to the result of the comparison.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.