Memory element, semiconductor device, and writing method
US9190166B2 · kind B2 · utility
3Cited by
1References
14Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jan 15, 2014 |
| Grant date | Nov 17, 2015 |
| Priority date | — |
| Expiry date | Jan 19, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory element includes: an electrical fuse provided to be inserted between a first input node and a second input node; and an antifuse provided to be inserted between the second input node and a third input node. The third input node is configured to be a node to which a voltage is allowed to be applied separately from a voltage to be applied to the first input node.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.